Biography

Mar. 1981 B.E. Department of Electronical Engineering, Faculty of Engineering, Yokohama National University.
Mar. 1983 M.E., Graduate School, Division of Engineering, Department of Computer Science, Yokohama National University.
Mar. 1986 D.E., Graduate School, Division of Engineering, Department of Electronic Engineering, the University of Tokyo.
Apr. 1986 Lecturer, School of Engineering, Yokohama National University.
Nov. 1989 Associate Professor, School of Engineering, Yokohama National University.
Mar. 2001 Professor, School of Engineering, Yokohama National University.

He is Chairperson of CRYPTREC Advisory Board for Cryptographic Technology, Chairperson of ISO/TC 68 Japanese Mirror Committee, Member of Science Council of Japan (SCJ), and Chairperson of Cybersecurity Research and Development Strategy Committee of National center of Incident readiness and Strategy for Cybersecurity (NISC), etc.

Paper

• Nano-artifact metrics based on random collapse of resist, Matsumoto, T. et al., Scientific Reports 4 (6142), 2014.08.
• Catching the Behavioral Differences between Multiple Executions for Malware Detection, Kasama Takahiro, Yoshioka Katsunari, Inoue Daisuke, Matsumoto Tsutomu, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, E96A (1) 225 – 232, 2013.01.
• A proper security analysis method for CMOS cryptographic circuits, Takahashi Yoshio, Matsumoto Tsutomu, IEICE ELECTRONICS EXPRESS, 9 (6) 458 – 463, 2012.03.
• Individuality evaluation for paper based artifact-metrics using transmitted light image, Manabu Yamakoshi, Junichi Tanaka, Makoto Furuie, Masashi Hirabayashi, IS&T/SPIE Electronic Imaging 2008, 2008.01.

Website

• Personal HP : https://er-web.ynu.ac.jp/html/MATSUMOTO_Tsutomu/en.html

Awards

• Achievement Award, IEICE, Japan, 1995.
• 5th DoCoMo Mobile Science Award, 2006.
• 4th Information Security Culture Award, 2008.
• Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology (Research), 2010, etc.