Naoya Torii

Naoya Torii

Biography

1981 B.S. degree in Communication Engineering from Osaka University, Japan
1983 M.S. degree in Communication Engineering from Osaka University, Japan
2017 Ph.D. in Engineering, Yokohama National University
1983-2018 Fujitsu Laboratories Ltd.
2018-2023 Professor, Graduate School of Science and Engineering, Soka University, Japan
2024-presrnt Invited Senior Researcher of Hardware Security Research Team, Cyber Physical Security Research Institute, National Institute of Advanced Industrial Science and Technology (AIST), Japan

Papers（Selective）

• Naoya Torii, Hirotaka Kokubo, Dai Yamamoto, Kouichi Itoh, Masahiko Takenaka, and Tsutomu Matsumoto, “ASIC implementation of random number generators using SR latches and its evaluation,” EURASIP J. on Info. Security, 2016, 10 (2016).
• Naoya Torii, Dai Yamamoto, Masahiko Takenaka, Tsutomu Matsumoto, "Experimental Evaluation on the Resistance of Latch PUFs Implemented on ASIC against FIB-Based Invasive Attacks," IEICE Trans. on Fundamentals, vol. E99-A, no. 1, pp. 118-129 (2016)
• Naoya Torii, Dai Yamamoto, Tsutomu Matsumoto, "Evaluation of Latch-based Physical Random Number Generator Implementation on 40 nm ASICs," TrustED '16: Proceedings of the 6th International Workshop on Trustworthy Embedded Devices pp.23-30 (2016)
• Souichi Okada, Naoya Torii, Kouichi Itoh, and Masahiko Takenaka, “Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2^m) on an FPGA,” CHES2000, LNCS vol. 1965, pp 25-40 Springer-Verlag (2000).
• Kouichi Itoh, Masahiko Takenaka, Naoya Torii, Syouji Temma, and Yasushi Kurihara, “Fast Implementation of Public-Key Cryptography on a DSP TMS320C6201,”CHES 1999, LNCS vol. 1717, pp 61-72 Springer-Verlag (1999).

Websites

• researchmap : https://researchmap.jp/7000026626
• Google Scholar : https://scholar.google.com/citations?hl=en&user=OAcO8bgAAAAJ