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- Hirofumi Sakane
Hirofumi Sakane
Biography
1990 B. Eng. in Electronics, Yamaguchi University.
1992 M. Eng. in Electro-communications, the Graduate School of Electro-Communications, the University of Electro-Communications.
1992 Joined Electro-Technical Laboratory
2001 Ph.D. in Information Engineering, the Graduate School of Electro-Communications, the University of Electro-Communications.
2001 Organizational change from Electro-Technical Laboratory to National Institute of Advanced Industrial Science and Technology.
2002-2005 Visiting scholar at University of Delaware
2008-2012 Guest researcher at National Institute of Standards and Technology
Research Area: Hardware security
Papers（Selective）
- Satoh, Katashita, Sakane: “”, Synthesiology, Vol.3, No.1, 2010．
- Katashita, Hori, Sakane, Satoh, Side-Channel Attack Standard Evaluation Board SASEBO-W for Smartcard Testing, Proc. NIAT Workshop, 2011.
- Hori, Katashita, Sakane, Toda, Satoh, Bitstream Protection in Dynamic Partial Reconfiguration Systems using Authenticated Encryption, IEICE Trans. Information and Systems, Vol.E96-D, No.11, pp.2333-2343, 2013.
- Ohsaki, Sakane, Handa: “Cybersecurity Requirements and the Certification of Smart-Meter Systems”, Safety Engineering, Vol.54, No.6, pp.442-451, 2015.
- Sakane, Kawamura, Imafuku, Hori, Nagata, Hayashi, Matsumoto: “Physical-Level Detection Approach against Hardware Trojans inside Semiconductor Chips (II)”, IEICE Technical Report, Vol. 120, No. 211, HWS2020-35, pp. 59-64, 2020.
Awards
- International Standard Development Award, ISO/IEC 20085-1, Information Technology Standards Commission of Japan, 2020
- International Standard Development Award, ISO/IEC 20085-2, Information Technology Standards Commission of Japan, 2020